The present invention relates to a capacitor and method for fabricating same, and, more particularly, relates to an interconnect level capacitor in an integrated circuit and method for fabricating same.
Capacitors are used extensively in electronic devices for storing an electric charge. The capacitors essentially comprise two conductive plates separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, is measured in farads and depends upon the area of the plates, the insulator thickness between them, and the dielectric constant of the insulator. Capacitors are used in filters, in analog-to-digital converters (ADCs), in memories, and in various control applications.
The integration of high value capacitors in integrated circuits is limited by the fact that conventional high value capacitors take up large areas of a chip and severely restrict interconnect routing in the region of the capacitor, thus reducing the device packing density and layout efficiency. Many applications, including telecommunications equipment, require a large number of capacitors, e.g., as coupling/decoupling capacitors and for filters.
Decoupling capacitors are used to decouple, or dampen, transient current spikes produced as a result of simultaneous switching of circuits on logic chips. Incorporating these decoupling capacitors as discrete off-chip components, substantially increases the bulk of the peripheral circuitry. Discrete decoupling capacitors are also very expensive. Another disadvantage is that as technology requires ever smaller components, such discrete capacitors must be miniaturized in order to fit in very small spaces. Fabrication of such small components is not always feasible.
Capacitors built into the integrated circuit chip eliminate the cost of discrete capacitor components. Capacitors built into integrated circuits are usually fabricated from polysilicon to polysilicon, metal to polysilicon, or metal to polycide structures. Providing decoupling capacitance in silicon by separate capacitor devices, takes up valuable silicon space. In dense chip areas, circuits are pushed apart to make room for the decoupling capacitors, resulting in longer interconnect lengths and reduced performance. Current metal-insulator-metal (MIM) capacitor structures comprise large area capacitors with limited capacitance per unit area. A further disadvantage is that such large area MIM capacitor structures consume excess chip space. In addition, present copper BEOL (back end of the line) technology cannot be used for large area capacitors due to CMP (chemical mechanical polishing) dishing process constraints.
U.S. Pat. No. 5,851,870 to Alugbin et al. provides a method for forming a capacitor for use in semiconductor integrated circuits, the capacitor including a metal-dielectric-metal stack formed within a window upon a conductive substrate. Alugbin et al. discloses contact to the top plate of the capacitor through a window within a window and contact to the bottom plate by a guard ring which contacts the conductive substrate. The method steps comprise forming a conductive substrate, forming a patterned dielectric upon the substrate, the patterned dielectric having an opening which exposes the substrate, the opening having at least one side, forming at least one conductive material within the opening, the conductive material contacting the substrate and not contacting the sides of the opening, forming a dielectric upon the conducting material, the dielectric not contacting the sides of the opening, and forming a conductive layer upon the dielectric layer, the conductive top layer not contacting the sides of the opening.
U.S. Pat. No. 5,789,303 to Leung et al. discloses a capacitor structure for an integrated circuit, comprising a bottom electrode, capacitor dielectric, and top electrode, formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization.
U.S. Pat. No. 5,339,313 to Geffken et al. provides a decoupling capacitor, and method for forming same, which utilizes a plurality of tungsten studs and metal interconnects to maximize the surface area of the capacitor, thereby increasing the capacitance. The metal interconnects only partially overlap the tungsten studs, forming the first plate of the capacitor, so that the tops of the studs as well as the sides and tops of the interconnects provide the increased surface area. The capacitor may comprise two or more capacitors stacked one on the other to form relative upper and lower capacitors. There remains a need for an improved interconnect level decoupling capacitor in an integrated circuit and an improved method for fabricating same.
The above-discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by the present capacitor and method wherein a capacitor structure is built into the interconnect wiring level of a chip, eliminating the need for additional discrete capacitor components and their associated expense. The present capacitor structure increases capacitance by utilizing the top, bottom and sidewall surface areas of the capacitor structure, providing a decoupling capacitor within a trench etched into an insulator layer provided on the interconnect level of the chip, thus providing decoupling capacitance without sacrificing valuable silicon space. The present integrated circuit interconnect level capacitor structure comprises a first insulator layer overlying an interconnect level surface of an integrated circuit; first and second conductive lines provided in said first insulator layer and separated by a trench defined by said first insulator layer; a first conductive barrier layer overlying and connecting said first and second conductive lines; a second insulator layer overlying said first conductive barrier layer; a second conductive barrier layer overlying said second insulator layer; and a third conductive line disposed in said trench and overlying said second conductive barrier layer.
The present method employs damascene processing and use of a conductive barrier layer to enable fabrication of more densely packed capacitors, while also providing the advantages of minimal processing steps and compatibility with current semiconductor processes and materials. Particularly, the present process provides the advantage of BEOL processing which can be added as an option to existing integrated circuit fabrication processes without necessitating changes in sequence operations.
The present method comprises forming an integrated circuit interconnect level capacitor by depositing a first insulator layer over an interconnect level surface of a semiconductor substrate having active devices; forming first and second conductive lines in said first insulator layer; etching said first insulator layer to form a trench in said first insulator layer between said first and second conductive lines; depositing a first conductive barrier layer over said first and second conductive lines and said trench; depositing a second interlevel insulator layer over said first conductive barrier layer; depositing a second conductive barrier layer over said second interlevel insulator layer; forming a third conductive line disposed in said trench and overlying said second conductive barrier layer. It is preferred that said first and second conductive lines in said first insulator layer be parallel in order to achieve maximum capacitance and surface area.